ZhanPeng Liu (Peking University), Chenyang Li (Peking University), Wende Tan (Imperial College London), Yuan Li (Zhongguancun Laboratory), Xinhui Han (Peking University), Xi Cao (Science City (Guangzhou) Digital Technology Group Co., Ltd.), Yong Xie (Qinghai University), Chao Zhang (Tsinghua University)

Modern software systems increasingly rely on compartmentalization to isolate untrusted or potentially vulnerable components, such as third-party drivers and JIT-compiled code.
However, existing hardware isolation techniques suffer from scalability constraints, high switching latency, and inadequate security guarantees. In particular, permission-changing instructions used by some compartmentalization technology, such as Intel MPK’s WRPKRU, can be exploited by untrusted code, which complicates the secure deployment process.

In this paper, we introduce LatticeBox, a hardware-software co-designed framework that addresses these limitations using a lattice-based access control model. LatticeBox encodes permissions and memory regions as compact, hierarchical N-bit vectors. This design enables a hardware architecture that reduces domain-switching latency to a single CPU cycle and inherently prevents misuse of permission-switching instructions. Additionally, LatticeBox employs a customized instruction (lp_land) to enforce strict cross-domain control-flow integrity, effectively preventing unauthorized indirect function calls. We implement LatticeBox on a RISC-V BOOM core and evaluate it using both microbenchmarks and real-world applications, including WebAssembly runtimes and Linux kernel modules. Our results show that LatticeBox achieves domain switching up to 180× faster than Intel MPK while supporting fine-grained, scalable isolation. Evaluation on real-world workloads demonstrates only a modest performance impact, with only 2% slowdown for enhanced WebAssembly runtimes and just 3% lower throughput for ApacheBench running isolated Linux kernel modules.

View More Papers

MES: Thwarting Fuzzing by Suppressing Memory Errors (Registered Report)

Fannv He (National Computer Network Intrusion Protection Center, University of Chinese Academy of Sciences, China, and School of Cyberspace Security, Hainan University, China), Yuan Liu (School of Cyber Engineering, Xidian University, China), Jice Wang (School of Cyberspace Security, Hainan University, China), Baiquan Wang (School of Cyberspace Security, Hainan University, China), Zezhong Ren (National Computer Network…

Read More

Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer

Johannes Lenzen (Technical University of Darmstadt), Mohamadreza Rostami (Technical University of Darmstadt), Lichao Wu (Technical University of Darmstadt), Ahmad-Reza Sadeghi (Technical University of Darmstadt)

Read More

Practical Traceable Over-Threshold Multi-Party Private Set Intersection

Le Yang (School of Cyber Science and Technology, University of Science and Technology of China), Weijing You (Fujian Provincial Key Laboratory of Network Security and Cryptology, College of Computer and Cyber Security, Fujian Normal University), Huiyang He (School of Cyber Science and Technology, University of Science and Technology of China), Kailiang Ji (NIO Inc), Jingqiang…

Read More